Re: [Bitcoin-development] New side channel attack that can recover Bitcoin keys

[Troy Benjegerdes <hozer@hozed.org>]

This *could* be a useful feature, but only if it's generalizable to
other processor architectures, and **in particular** has an implementation
using dedicated silicon that has a **public** open-source hardware layout,
so you can X-ray the chip, and confirm with a thermal imager that yes, the
encryption code is actually running where you think it's running.

I was *almost* convinced that the 'new key per address' was a good idea
to mitigate ECDSA side channel attacks. Now, however, I find it quite 
plausible that intelligence agencies are promoting 'new key per transaction'
as a way to make sure all your keys are leaked all over RAM and the nearby
electromagnetic spectrum with side channels intentionally embedded in
commodity hardware.

If you want to convince me otherwise, then help me crowdfund an open-source
hardware Bitcoin ASIC that does the crypto and stores your private keys. 

I expect the 'new key per transaction' crowd will be in for a rude awakening
when they finally understand the silicon area cost to do this securely.

Conclusion: Not only is 'de-prioritizing address re-use' BAD privacy, it 
provides a social engineering/key leakage attack vector where someone can
track you down from the EMF generated by your bitcoin wallet when they send
you money.

If you think otherwise, let's build some ficking open-source hardware and 
find out how much silicon this will cost.

Although it's probably more profitable to just build a bitcoin wallet 
detector and keep your mouth shut.

On Thu, Mar 06, 2014 at 11:00:14AM +0100, Natanael wrote:
> You've heard of TRESOR?
> 
> No, not Trezor.
> 
> https://en.wikipedia.org/wiki/TRESOR
> 
> Signing on the CPU, without touching RAM.
> 
> - Sent from my phone
> Den 6 mar 2014 09:41 skrev "Mike Hearn" <mike@plan99.net>:
> 
> > I'm wondering about whether (don't laugh) moving signing into the kernel
> > and then using the MTRRs to disable caching entirely for a small scratch
> > region of memory would also work. You could then disable pre-emption and
> > prevent anything on the same core from interrupting or timing the signing
> > operation.
> >
> > However I suspect just making a hardened secp256k1 signer implementation
> > in userspace would be of similar difficulty, in which case it  would
> > naturally be preferable.
> >
> >
> > On Wed, Mar 5, 2014 at 11:25 PM, Gregory Maxwell <gmaxwell@gmail.com>wrote:
> >
> >> On Wed, Mar 5, 2014 at 2:14 PM, Eric Lombrozo <elombrozo@gmail.com>
> >> wrote:
> >> > Everything you say is true.
> >> >
> >> > However, branchless does reduce the attack surface considerably - if
> >> nothing else, it significantly ups the difficulty of an attack for a
> >> relatively low cost in program complexity, and that might still make it
> >> worth doing.
> >>
> >> Absolutely. I believe these things are worth doing.
> >>
> >> My comment on it being insufficient was only that "my signer is
> >> branchless" doesn't make other defense measures (avoiding reuse,
> >> multsig with multiple devices, not sharing hardware, etc.)
> >> unimportant.
> >>
> >> > As for uniform memory access, if we avoided any kind of heap
> >> allocation, wouldn't we avoid such issues?
> >>
> >> No. At a minimum to hide a memory timing side-channel you must perform
> >> no data dependent loads (e.g. no operation where an offset into memory
> >> is calculated). A strategy for this is to always load the same values,
> >> but then mask out the ones you didn't intend to read... even that I'd
> >> worry about on sufficiently advanced hardware, since I would very much
> >> not be surprised if the processor was able to determine that the load
> >> had no effect and eliminate it! :) )
> >>
> >> Maybe in practice if your data dependencies end up only picking around
> >> in the same cache-line it doesn't actually matter... but it's hard to
> >> be sure, and unclear when a future optimization in the rest of the
> >> system might leave it exposed again.
> >>
> >> (In particular, you can't generally write timing sign-channel immune
> >> code in C (or other high level language) because the compiler is
> >> freely permitted to optimize things in a way that break the property.
> >> ... It may be _unlikely_ for it to do this, but its permitted— and
> >> will actually do so in some cases—, so you cannot be completely sure
> >> unless you check and freeze the toolchain)
> >>
> >> > Anyhow, without having gone into the full details of this particular
> >> attack, it seems the main attack point is differences in how squaring and
> >> multiplication (in the case of field exponentiation) or doubling and point
> >> addition (in the case of ECDSA) are performed. I believe using a branchless
> >> implementation where each phase of the operation executes the exact same
> >> code and accesses the exact same stack frames would not be vulnerable to
> >> FLUSH+RELOAD.
> >>
> >> I wouldn't be surprised.
> >>
> >>
> >> ------------------------------------------------------------------------------
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> >>
> >
> >
> >
> > ------------------------------------------------------------------------------
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> >

> ------------------------------------------------------------------------------
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> freedom to use Git, Perforce or both. Make the move to Perforce.
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-- 
----------------------------------------------------------------------------
Troy Benjegerdes                 'da hozer'                  hozer@hozed.org
7 elements      earth::water::air::fire::mind::spirit::soul        grid.coop

      Never pick a fight with someone who buys ink by the barrel,
         nor try buy a hacker who makes money by the megahash